Welcome to ASIC/FPGA Chip Design Course Website (Spring 2018): (Last Updated: 05-12-2018)

I. Instructor: Mahdi Shabany

II. Objective:

This course provides comprehensive theoretical understanding as well as exciting hands‐on practical experience of the digital design flow, including the architecture optimization, hardware description languages (Verilog Coding), commercial Programmable Logic Devices (PLDs) and Field Programmable Gate Arrays (FPGAs) architectures, the physical realization steps in digital custom Application Specific Integrated Circuits (ASICs) design, as well as synthesis algorithms. Students will earn invaluable experience to professionally work with state‐of‐the‐art design tools for both FPGA and ASIC design flow through several hardware implementation assignments. The implementation platform is Altera DE2 board as well as Xilinx standard boards, which will be used throughout the course. Moreover, students will design a ready for‐fabrication ASIC as a final project in this course.

III. Lecture Notes:

●  Introduction (02-04-2017)

●  Verilog Coding (02-14-2017)

●  Verilog for Synthesis (03-17-2017)

●  Verification (04-07-2017)

●  FPGA Architectures (04-07-2017)

●  CORDIC Theory and Implementation (05-21-2017)

●  Synthesis Algorithms (05-21-2017)

●  Power Dissipation (05-21-2017)

●  Power Grid and Clock Design (05-21-2017)

●  Fixed-point Simulation Methodology (05-21-2017)

●  ASIC Design Flow

●  Core Generator

IV. Assignments:

● Assignment #0 (02-04-2017)

● Assignment #1 (02-07-2017)

● Assignment #2 (02-22-2017)

● Assignment #3 (03-14-2018)

● Assignment #4 (04-15-2018)

●  Assignment #5 : Workshop Lab 1,2

●  Assignment #6 : Workshop Lab 3,4,5

●  Assignment #7 : Workshop Lab 6,7,8

● Assignment #8 (05-12-2018)

●  Assignment #9

V. Tutorials

●  ISE

●  ISE Tutorial

●  XST Manual (Coding techniques for synthesis)

●  Quartus:

●  Part I

●  Part II

●  Part III

●  Library of parameterizes modules (LPMs)

●  Modelsim:

●  Please note that you need to install Modelsim on your machine. It is recommended to do the following tutorial.

●  License

●  Read this file first.

●  Modelsim Tutorial

●  There are two files used in this tutorial, which you can download from here, test.v, test_tb.v. Please copy them in the work directory you want to run the Modelsim tutorial. Please note that these files are used instead of the files suggested by the Modelsim tutorial in page T-19 of the tutorial.

●  Necessary files to learn reading and writing files in Modelsim. Download it here.

VI. Labs:

●  Lab Schedule (3-14-2018)

VII. DE2 Board Documents: (02-02-2013)

●  DE2 Board Installation (required on your notebook)

●  DE2 Board Manual

VIII. References:

1) Verilog:

●  Introduction to Logic Synthesis using Verilog HDL, Robert Reese, Mitchell Thornton, 2006.

●  Fundamentals of Digital Logic with Verilog Design, 2nd Edition, [Appendix A: Verilog], S. Brown, 2006.

●  Verilog Coding for Logic Synthesis, Weng Fook Lee , 2003.

●  Verilog HDL Synthesis, A Practical Primer by J. Bhasker, 1998

●  ASIC World Verilog (Useful tutorials/examples)

●  Signed Arithmetic in Verilog 2001-Opportunities and Hazards

●  CORDIC Theory and Implementation

2) FPGA Architectures:

●  Architecture of FPGAs and CPLDs: A Tutorial, Stephen Brown, Jonathan Rose, 2006.

●  Advanced FPGA Design, Architecture, Implementation, and Optimization, Steve Kilts, 2007.

●  FPGA Architecture: Survey and Challenges, Ian Kuon, Russell Tessier, Jonathan Rose, 2008.

●  ISE Tutorial, Xilinx.

●  FPGA-Based System Design, Wayne Wolf.

●  Virtex 4, and Virtex 5 Structure

3) Logic Synthesis:

� Technology Mapping

1. An intro to dynamic programming can be found in chapter 15 of T.H. Cormen, C.E. Leiserson, R.L. Rivest, "Introduction To Algorithms - Second Edition", McGraw-Hill, 2001.

2. A clear overview of dynamic programming, with a few examples, can be found in Wikipedia (here)

3. A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUT-based FPGAs", to appear in  IEEE Transactions on CAD, 2007.  (PDF)

4. K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," ACM/IEEE Design Automation Conference, 1987, pp. 341-347. (PDF)

5. J.H. Anderson and F. N. Najm, "Power-Aware Technology Mapping for LUT-Based FPGAs," IEEE International Conference on Field-Programmable Technology (FPT), Hong Kong, 2002, pp. 211 - 218.

6. K. C. Chen, J. Cong, Y. Ding, A. B. Kahng and P. Trajmar, "DAG-MAP: Graph Based FPGA Technology Mapping For Delay Optimization", IEEE Design and Test, September 1992, pp. 7-20. (PDF) (describes how to break an arbitrary Boolean Network into smaller k-input functions)

4) Physical Design:

� An Introduction to VLSI Physical Design, Majid Sarrafzadeh, 1996.

� Floorplanning (Sequence Pair/Linear Programming)

1. Jae-Gon Kim; Yeong-Dae Kim, "A linear programming-based algorithm for floorplanning in VLSI design," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.22, no.5, pp. 584-592, May 2003  (PDF)

2. For linear programming, you can Google it to find many resources or you may consult a standard text.  I like this on-line book: http://www.sce.carleton.ca/faculty/chinneck/po.html

3. H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair", IEEE Transactions on CAD, pp 1518-1524, 1996. (PDF)

4. H. H. Chan, S. N. Adya, I. L. Markov, "Are Floorplan Representations Useful in Digital Design?",  ACM/IEEE International Symposium on Physical Design, 2005. (PDF)

5. D. F. Wong, C. L. Liu, "A New Algorithm for Floorplan Design" ACM/IEEE Design Automation Conference, pp 101-107, 1986. (optional: classic paper) (PDF)

� Placement (Simulated Annealing)

1. S. Kirkpatrick, C. Gellat, M. Vecchi, "Optimization by simulated annealing," Science, 220:671-680, 1983. (PDF)

2. C. Sechen, A. Sangiovanni-Vincentelli, "The TimberWolf placement and routing package," IEEE Journal of Solid State Circuits, Vol. 20, No. 2, pp. 432-439, 1985. (PDF)

3. V. Betz, J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," International Workshop on Field-Programmable Logic and Applications, London, UK, 1997, pp. 213 - 222. (PDF)

4. Chih-liang Eric Cheng, "Risa: Accurate And Efficient Placement Routability Modeling," Computer-Aided Design, 1994., IEEE/ACM International Conference on , vol., no., pp.690-695, 6-10 Nov 1994. (PDF)

� Placement (Analytical Techniques)

1. Viswanathan, N.; Chu, C.C.-N., "FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.24, no.5, pp. 722-733, May 2005  (PDF)

2. Hans Eisenmann, Frank M. Johannes,"Generic global placement and floorplanning,� ACM/IEEE Design Automaton Conference, 1998, pp. 269-274. (PDF)

3. K. P. Vorwerk, A. Kennings, A. Vannelli, "Engineering details of a stable force-directed placer", IEEE/ACM International Conference on Computer-Aided Design, 2004, pp. 573-580. (PDF)

4. J. M. Kleinhans, G. Sigl, F. M. Johannes, K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization, " IEEE Transactions on CAD, Vol. 10, No. 3, pp. 356-365, 1991. (classic paper) (PDF)

5. Natarajan Viswanathan, Gi-Joon Nam, Charles Alpert, Paul Villarrubia, Haoxing Ren, and Chris Chu, RQL: Global Placement via Relaxed Quadratic Spreading and Linearization IEEE/ACM Design Automation Conference, pages 453-458, 2007. (PDF)

� Detailed Routing (applied to FPGAs)

1. C.Y. Lee, "An algorithm for path connections and its applications," IRE Transactions on Electronic Computers,vol. 10, pp. 346-365, Sept. 1961.

2. See Section III-D of: M.A. Breuer, M. Sarrafzadeh, F. Somenzi, "Fundamental CAD algorithms," IEEE Transactions on CAD, Vol. 19, No. 12, pp. 1449-1475, December 2000 (PDF)

3. J.S. Rose, S.D. Brown, "Flexibility of interconnection structures for field-programmable gate arrays", IEEE Journal of Solid State Circuits, Vol. 26 No. 3, pp. 277-282, March 1991. (classic paper) (PDF)

4. S.D. Brown, J.S. Rose, Z.G. Vranesic, "A detailed router for field-programmable gate arrays," IEEE Transactions on CAD, Vol. 11, No. 5, pp. 620-628, May 1992. (PDF)

5. S.J.E. Wilton, ``A Crosstalk-Aware Timing-Driven Router for FPGAs'',ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb. 2001 (PDF).

6. Yajun Ran, Malgorzata Marek-Sadowska, "Crosstalk noise in FPGAs", ACM/IEEE Design Automation Conference, 2003 (PDF)

� Timing-Driven Routing

1. Ravi Nair, "A simple yet effective technique for global wiring," IEEE Transactions on CAD, Vol. 6, No. 2, pp. 165-172, 1987. (PDF)

2. J. Rubenstein, P. Penfield, M. A. Horowitz,"Signal delay in RC tree networks,�IEEE Transactions on CAD, vol. 2, no. 3, pp. 202-211, July 1983. (PDF)

3. W.C. Elmore, "The transient response of damped linear networks," Journal of Applied Physics, Vol. 19, pp. 55-63, January 1948.

4. Larry McMurchie, Carl Ebeling. "PathFinder: A negotiation-based performance-driven router for FPGAs," ACM International Symposium on Field Programmable Gate Arrays, pp. 111-117, 1995. (PDF)

5. R. Fung, V. Betz, and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations," IEEE Trans. on Computer-Aided Design of Circuits and Systems, April 2008, pp. 686 - 697. (PDF)

6. Moffitt, M. D., Roy, J. A., and Markov, I. L. 2008. The coming of age of (academic) global routing. In Proceedings of the 2008 international Symposium on Physical Design (Portland, Oregon, USA, April 13 - 16, 2008). ISPD '08. pp. 148-155. (PDF)

7. Hadsell, R.T.; Madden, P.H., "Improved global routing through congestion estimation," Design Automation Conference, 2003. Proceedings , pp. 28-31, 2-6 June 2003  (PDF)